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19-3273; Rev 1; 7/04
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock
General Description
The MAX7033 fully integrated low-power CMOS superheterodyne receiver is ideal for receiving amplitudeshift-keyed (ASK) data in the 300MHz to 450MHz frequency range. The receiver has an RF input signal range of -114dBm to 0dBm. With few external components and a low-current power-down mode, it is ideal for cost-sensitive and power-sensitive applications typical in the automotive and consumer markets. The MAX7033 consists of a low-noise amplifier (LNA), a fully differential image-rejection mixer, an on-chip phaselocked loop (PLL) with integrated voltage-controlled oscillator (VCO), a 10.7MHz IF limiting amplifier stage with received-signal-strength indicator (RSSI), and analog baseband data-recovery circuitry. The MAX7033 also has a discrete one-step automatic gain control (AGC) that reduces the LNA gain by 35dB when the RF input signal exceeds -62dBm. The AGC circuitry offers an externally controlled hold feature. The MAX7033 is available in a 28-pin TSSOP package and is specified over the extended (-40C to +105C) temperature range.
Features
Optimized for 315MHz or 433MHz Band Operates from Single +3.3V or +5.0V Supplies High Dynamic Range with On-Chip AGC AGC Hold Circuit 1ms AGC Release Time Selectable Image-Rejection Center Frequency Selectable x64 or x32 fLO/fXTAL Ratio Low 5.2mA Operating Supply Current <3.5A Low-Current Power-Down Mode for Efficient Power Cycling 250s Startup Time Built-In 44dB RF Image Rejection Better than -114dBm Receive Sensitivity -40C to +105C Operation
MAX7033
Applications
Automotive Remote Keyless Entry Security Systems Garage Door Openers Home Automation Remote Controls Local Telemetry Wireless Sensors
PART MAX7033EUI MAX7033ETJ*
Ordering Information
TEMP RANGE -40C to +105C -40C to +105C PIN-PACKAGE 28 TSSOP 32 Thin QFN-EP**
Typical Application Circuit appears at end of data sheet.
*Future product--contact factory for availability. **EP = Exposed paddle.
Pin Configurations
LNASRC LNAIN
PDOUT
XTAL1
XTAL2
SHDN
TOP VIEW
XTAL1 1 AVDD 2 LNAIN 3 LNASRC 4 AGND 5 LNAOUT 6 AVDD 7 MIXIN1 8 MIXIN2 9 AGND 10 IRSEL 11 MIXOUT 12 DGND 13 DVDD 14 28 XTAL2 27 SHDN 26 PDOUT 25 DATAOUT 24 VDD5
AVDD
32
31
30
29
28
27
26
25 24 23 22 21
N.C.
N.C. AGND LNAOUT AVDD MIXIN1 MIXIN2 AGND IRSEL
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16
DATAOUT VDD5 DSP N.C. DFFB OPP DSN DFO
MAX7033
23 DSP 22 DFFB 21 OPP 20 DSN 19 DFO 18 IFIN2 17 IFIN1 16 XTALSEL 15 AC
MAX7033
20 19 18 17
MIXOUT
9
DGND
TSSOP
THIN QFN
________________________________________________________________ Maxim Integrated Products
XTALSEL
DVDD
IFIN1
IFIN2
N.C.
AC
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033
ABSOLUTE MAXIMUM RATINGS
VDD5 to AGND.......................................................-0.3V to +6.0V AVDD to AGND ......................................................-0.3V to +4.0V DVDD to DGND......................................................-0.3V to +4.0V AGND to DGND.....................................................-0.1V to +0.1V IRSEL, DATAOUT, XTALSEL, AC, SHDN to AGND .............................-0.3V to (VDD5 + 0.3V) All Other Pins to AGND............................-0.3V to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 28-Pin TSSOP (derate 12.8mW/C above +70C) ..1025.6mW 32-Thin QFN (derate 21.3mW/C above +70C) ....1702.1mW Operating Temperature Range .........................-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering 10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (+3.3V OPERATION)
(Typical Application Circuit, AVDD = DVDD = VDD5 = +3.0V to +3.6V, no RF signal applied, TA = -40C to +105C, unless otherwise noted. Typical values are at AVDD = DVDD = VDD5 = +3.3V and TA = +25C.) (Note 1)
PARAMETER Supply Voltage Supply Current Shutdown Supply Current Input-Voltage Low Input-Voltage High Input Logic Current High SYMBOL AVDD, DVDD IDD ISHDN VIL VIH IIH fRF = 433MHz, VIRSEL = VDD5 Image-Reject Select Voltage (Note 2) fRF = 375MHz, VIRSEL = VDD5 / 2 fRF = 315MHz, VIRSEL = 0V DATAOUT Output-Voltage Low DATAOUT Output-Voltage High VOL VOH ISINK = 10A ISOURCE = 10A 0.125 DVDD 0.125 VDD5 0.4 1.1 VDD5 1.0 0.4 V V V DVDD 0.4 10 CONDITIONS +3.3V nominal supply voltage V SHDN = DVDD V SHDN = 0V, VXTALSEL = 0V fRF = 315MHz fRF = 433MHz fRF = 315MHz fRF = 433MHz MIN 3.0 TYP 3.3 5.2 5.7 2.6 3.5 8.0 0.4 MAX 3.6 6.23 6.88 UNITS V mA A V V A
DC ELECTRICAL CHARACTERISTICS (+5.0V OPERATION)
(Typical Application Circuit, VDD5 = +4.5V to +5.5V, no RF signal applied, TA = -40C to +105C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25C.) (Note 1)
PARAMETER Supply Voltage Supply Current Shutdown Supply Current Input-Voltage Low SYMBOL VDD5 IDD ISHDN VIL CONDITIONS +5.0V nominal supply voltage V SHDN = VDD5 V SHDN = 0V, VXTALSEL = 0V fRF = 315MHz fRF = 433MHz fRF = 315MHz fRF = 433MHz MIN 4.5 TYP 5.0 5.2 5.7 3.7 4.2 9.0 0.4 MAX 5.5 6.4 6.76 UNITS V mA A V
2
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315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock
DC ELECTRICAL CHARACTERISTICS (+5.0V OPERATION) (continued)
(Typical Application Circuit, VDD5 = +4.5V to +5.5V, no RF signal applied, TA = -40C to +105C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25C.) (Note 1)
PARAMETER Input-Voltage High Input Logic Current High SYMBOL VIH IIH fRF = 433MHz, VIRSEL = VDD5 Image-Reject Select Voltage (Note 2) fRF = 375MHz, VIRSEL = VDD5 / 2 fRF = 315MHz, VIRSEL = 0V DATAOUT Output-Voltage Low DATAOUT Output-Voltage High VOL VOH ISINK = 10A ISOURCE = 10A 0.125 VDD5 0.125 VDD5 0.4 1.1 VDD5 1.5 0.4 V V V CONDITIONS MIN VDD5 0.4 15 TYP MAX UNITS V A
MAX7033
AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, AVDD = DVDD = VDD5 = +3.0V to +3.6V, all RF inputs are referenced to 50, fRF = 315MHz, TA = -40C to +105C, unless otherwise noted. Typical values are at AVDD = DVDD = VDD5 = +3.3V and TA = +25C.) (Note 1)
PARAMETER GENERAL CHARACTERISTICS Startup Time Receiver Input Frequency Maximum Receiver Input Level Sensitivity (Note 3) AGC Hysteresis Maximum Data Rate LNA IN HIGH-GAIN MODE fRF = 433MHz Input Impedance 1dB Compression Point Input-Referred 3rd-Order Intercept LO Signal Feedthrough to Antenna Output Impedance Noise Figure ZOUT_LNA NFLNA Normalized to 50 ZIN_LNA P1dBLNA IIP3LNA Normalized to 50 fRF = 375MHz fRF = 315MHz 1 - j3.4 1 - j3.9 1 - j4.7 -22 -12 -80 0.12 - j4.4 3 dB dBm dBm dBm tON fRF Modulation depth >18dB Average carrier power level Peak power level LNA gain from low to high Switching time from low to high gain Manchester coded NRZ coded Time for valid signal detection after V SHDN = DVDD 300 0 -120 -114 8 1 33 66 250 450 s MHz dBm dBm dB ms kbps SYMBOL CONDITIONS MIN TYP MAX UNITS
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3
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, AVDD = DVDD = VDD5 = +3.0V to +3.6V, all RF inputs are referenced to 50, fRF = 315MHz, TA = -40C to +105C, unless otherwise noted. Typical values are at AVDD = DVDD = VDD5 = +3.3V and TA = +25C.) (Note 1)
PARAMETER LNA IN LOW-GAIN MODE Input Impedance 1dB Compression Point Input-Referred 3rd-Order Intercept LO Signal Feedthrough to Antenna Output Impedance Noise Figure Voltage-Gain Reduction MIXER Input Impedance Input-Referred 3rd-Order Intercept Output Impedance Noise Figure Image Rejection (Not Including LNA Tank) ZIN_MIX IIP3MIX ZOUT_MIX NFMIX fRF = 433MHz, VIRSEL = DVDD fRF = 375MHz, VIRSEL = DVDD / 2 fRF = 315MHz, VIRSEL = 0V LNA in high-gain mode LNA/Mixer Voltage Gain 330 IF filter load LNA in low-gain mode INTERMEDIATE FREQUENCY (IF) Input Impedance Operating Frequency 3dB Bandwidth RSSI Linearity RSSI Dynamic Range RSSI Level AGC Threshold DATA FILTER Maximum Bandwidth DATA SLICER Comparator Bandwidth 100 kHz 50 kHz PRFIN < -120dBm PRFIN > 0dBm, AGC enabled LNA gain from low to high LNA gain from high to low ZIN_IF fIF Bandpass response 330 10.7 10 0.5 80 1.15 2.2 1.39 1.98 MHz MHz dB dB V V 13 Normalized to 50 0.25 - j2.4 -18 330 16 42 44 44 48 dB dB dBm dB ZOUT_LNA NFLNA AGC enabled (depends on tank Q) Normalized to 50 ZIN_LNA P1dBLNA IIP3LNA Normalized to 50 (Note 4) fRF = 433MHz fRF = 375MHz fRF = 315MHz 1 - j3.4 1 - j3.9 1 - j4.7 -10 -7 -80 0.4 3 35 dB dB dBm dBm dBm SYMBOL CONDITIONS MIN TYP MAX UNITS
4
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315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, AVDD = DVDD = VDD5 = +3.0V to +3.6V, all RF inputs are referenced to 50, fRF = 315MHz, TA = -40C to +105C, unless otherwise noted. Typical values are at AVDD = DVDD = VDD5 = +3.3V and TA = +25C.) (Note 1)
PARAMETER Maximum Load Capacitance Output High Voltage Output Low Voltage CRYSTAL OSCILLATOR fRF = 433MHz Crystal Frequency (Note 5) fXTAL fRF = 315MHz Crystal Tolerance Input Capacitance From each pin to ground VXTALSEL = 0V VXTALSEL = VDD5 VXTALSEL = 0V VXTALSEL = VDD5 6.6128 13.2256 4.7547 9.5094 50 6.2 ppm pF MHz SYMBOL CLOAD CONDITIONS MIN TYP 10 VDD5 0 MAX UNITS pF V V
MAX7033
Note 1: 100% tested at TA = +25C. Guaranteed by design and characterization over temperature. Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image-rejection setting is desired. Bypass to AGND with a 1nF capacitor in a noisy environment. Note 3: BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz. Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance includes the 15nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is 50 in series with 2.2pF. Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (fRF - 10.7MHz) / 64 for XTALSEL = 0V, and (fRF - 10.7MHz) / 32 for XTALSEL = VDD5.
Typical Operating Characteristics
(Typical Application Circuit , AVDD = DVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7033 toc01
SUPPLY CURRENT vs. RF FREQUENCY
6.5 +105C SUPPLY CURRENT (mA) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 0.01 250 300 350 400 450 500 -40C +25C +85C
MAX7033 toc02
BIT-ERROR RATE vs. PEAK RF INPUT POWER
MAX7033 toc03
6.0 5.8 5.6 SUPPLY CURRENT (mA) 5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 3.0 3.1 3.2 3.3 3.4 3.5 -40C +25C +85C +105C
7.0
100 fRF = 433MHz BIT-ERROR RATE (%) 10
1
fRF = 315MHz
0.1
3.6
-130 -128 -126 -124 -122 -120 -118 -116 -114 PEAK RF INPUT POWER (dBm)
SUPPLY VOLTAGE (V)
RF FREQUENCY (MHz)
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5
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033
Typical Operating Characteristics (continued)
(Typical Application Circuit , AVDD = DVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25C, unless otherwise noted.)
RSSI AND DELTA vs. IF INPUT POWER
MAX7033 toc05
SENSITIVITY vs. TEMPERATURE
MAX7033 toc04
RSSI vs. RF INPUT POWER
2.4 IF BANDWIDTH = 280kHz 2.2 2.0 VAC = DVDD 2.4 2.2 2.0 RSSI (V) 1.8 1.6 1.4
-108 -110 -112 SENSITIVITY (dBm) PEAK RF INPUT POWER 0.2% BER IF BANDWIDTH = 280kHz fRF = 433MHz
MAX7033 toc06
3.5 2.5 1.5 0.5 DELTA (%)
RSSI (V)
-114 -116 -118 -120 -122 -124 -40 -15 10
1.8 1.6 1.4 VAC = 0V
DELTA
-0.5 -1.5
fRF = 315MHz 1.2 1.0 35 60 85 110 -140 -120 -100 -80 -60 -40 -20 0 TEMPERATURE (C) RF INPUT POWER (dBm) 1.2 1.0 -90 -70
RSSI -2.5 -3.5 -50 -30 -10 10 IF INPUT POWER (dBm)
LNA/MIXER VOLTAGE GAIN vs. IF FREQUENCY
MAX7033 toc07
IMAGE REJECTION vs. RF FREQUENCY
MAX7033 toc08
IMAGE REJECTION vs. TEMPERATURE
44.5 IMAGE REJECTION (dB) 44.0 43.5 43.0 42.5 42.0 41.5 fRF = 433MHz fRF = 375MHz fRF = 315MHz
MAX7033 toc09
65 55 SYSTEM GAIN (dB) 45 35 25 15 5 -5 0 5 10 15 20 25 FROM RFIN TO MIXOUT fRF = 315MHz 49dB IMAGE REJECTION LOWER SIDEBAND UPPER SIDEBAND
55
45.0
50 IMAGE REJECTION (dB)
45
40
fRF = 375MHz
35 fRF = 433MHz 30 30
fRF = 315MHz
41.0 40.5 -40 -15 10 35 60 85
280 300 320 340 360 380 400 420 440 460 480 RF FREQUENCY (MHz)
IF FREQUENCY (MHz)
TEMPERATURE (C)
6
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315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock
Typical Operating Characteristics (continued)
(Typical Application Circuit , AVDD = DVDD = VDD5 = +3.3V, fRF = 315MHz, TA = +25C, unless otherwise noted.)
NORMALIZED IF GAIN vs. IF FREQUENCY
MAX7033 toc10
MAX7033
S11 LOG MAGNITUDE PLOT OF RFIN
40 30 S11 MAGNITUDE (dB) 20 10 0 -10 -20 -30 315MHz -36dB
MAX7033 toc11
S11 SMITH CHART PLOT OF RFIN
MAX7033 toc12
5 0 NORMALIZED IF GAIN (dB) -5 -10 -15 -20 -25 -30 1 10 IF FREQUENCY (MHz)
50
WITH INPUT MATCHING 315MHz
500MHz
200MHz
-40 -50 100 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz)
REGULATOR VOLTAGE vs. REGULATOR CURRENT
MAX7033 toc13
PHASE NOISE vs. OFFSET FREQUENCY
MAX7033 toc14
PHASE NOISE vs. OFFSET FREQUENCY
fRF = 433MHz -20 PHASE NOISE (dBc/Hz) -40 -60 -80 -100 -120 -140
MAX7033 toc15
3.5 3.3 REGULATOR VOLTAGE (V) 3.1 2.9 2.7 2.5 2.3 2.1 1.9 1.7 0 10 20 30 40 50 -40C +25C +85C +105C
0 fRF = 315MHz -20 PHASE NOISE (dBc/Hz) -40 -60 -80 -100 -120 -140
0
60
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
REGULATOR CURRENT (mA)
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
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7
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033
Pin Description
PIN TSSOP 1 THIN QFN 29 NAME XTAL1 FUNCTION Crystal Input 1 (See the Phase-Locked Loop section) Positive Analog Supply Voltage. For +5V operation, AVDD is connected to an on-chip +3.2V low-dropout regulator. Both AVDD pins must be externally connected to each other. Bypass each pin to AGND with a 0.01F capacitor as close to the pin as possible (see the Typical Application Circuit). Low-Noise Amplifier Input (See the Low-Noise Amplifier section) Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set the LNA input impedance (see the Low-Noise Amplifier section). Analog Ground Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter (see the LowNoise Amplifier section). 1st Differential Mixer Input. Connect to LC tank filter from LNAOUT. 2nd Differential Mixer Input. Connect through a 100pF capacitor to AVDD side of the LC tank. Image-Rejection Select. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL unconnected to center image rejection at 375MHz. Set VIRSEL = VDD5 to center image rejection at 433MHz. 330 Mixer Output. Connect to the input of the 10.7MHz bandpass filter. Digital Ground Positive Digital Supply Voltage. Connect to AVDD. Bypass to DGND with a 0.01F capacitor as close to the pin as possible. Automatic Gain Control. See Figure 1. Internally pulled down to AGND with a 100k resistor. Crystal Divider Ratio Select. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL high to select divider ratio of 32. 1st Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF capacitor as close to the pin as possible. 2nd Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz bandpass filter. Data Filter Output Negative Data Slicer Input Noninverting Op-Amp Input for the Sallen-Key Data Filter Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter. Positive Data Slicer Input +5V Supply Voltage. For +5V operation, VDD5 is the input to an on-chip voltage regulator whose +3.2V output drives AVDD. Peak-Detector Output
2, 7
4, 30
AVDD
3 4 5, 10 6 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
31 32 2, 7 3 5 6 8 9 10 11 12 14 15 16 17 18 19 20 22 23 24 26
LNAIN LNASRC AGND LNAOUT MIXIN1 MIXIN2 IRSEL MIXOUT DGND DVDD AC XTALSEL IFIN1 IFIN2 DFO DSN OPP DFFB DSP VDD5
DATAOUT Digital Baseband Data Output PDOUT
8
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315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock
Pin Description (continued)
PIN TSSOP 27 28 -- THIN QFN 27 28 1, 13, 21, 25 NAME SHDN XTAL2 N.C FUNCTION Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a 100k resistor. Crystal Input 2. Can also be driven with an external reference oscillator. (See the Crystal Oscillator section.) No Connection
MAX7033
Functional Diagram
LNASRC 4 AC 15 LNAOUT 6 MIXIN1 MIXIN2 8 9 IRSEL 11 MIXOUT 12 IFIN1 17 IFIN2 18 28-PIN TSSOP PACKAGE
LNAIN
3
LNA
AUTOMATIC GAIN CONTROL
0 Q IMAGE REJECTION 90
IF LIMITING AMPS
MAX7033 RSSI DATA FILTER RDF2 100k RDF1 100k
AVDD VDD5 DVDD
2, 7 24 3.2V REG I
14
DIVIDE BY 64 PHASE DETECTOR /1 /2 16 XTALSEL 1
VCO
DGND
13
LOOP FILTER CRYSTAL DRIVER 28 POWERDOWN 27 SHDN 25 DATAOUT DATA SLICER
AGND
5, 10
20
23
19
26 PDOUT
21 OPP
22 DFFB
XTAL1 XTAL2
DSN DSP DFO
Detailed Description
The MAX7033 CMOS superheterodyne receiver and a few external components provide the complete receive chain from the antenna to the digital output data. Depending on signal power and component selection, data rates as high as 33kbps Manchester (66kbps NRZ) can be achieved. The MAX7033 is designed to receive binary ASK data modulated in the 300MHz to 450MHz frequency range. ASK modulation uses a difference in amplitude of the carrier to represent logic 0 and logic 1 data.
For operation with a single +4.5V to +5.5V supply voltage, connect VDD5 to the supply voltage. An on-chip voltage regulator drives one of the AV DD pins to approximately +3.2V. For proper operation, DVDD and both AVDD pins must be connected together. Bypass DV DD and both AV DD pins to AGND with 0.01F capacitors placed as close to the pins as possible.
Low-Noise Amplifier
The LNA is an nMOS cascode amplifier with off-chip inductive degeneration, with a 3.0dB noise figure and an IIP3 of -12dBm. The gain and noise figures are dependent on both the antenna matching network at the LNA input and the LC tank network between the LNA output and the mixer inputs.
Voltage Regulator
For operation with a single +3.0V to +3.6V supply voltage, connect AVDD, DVDD, and VDD5 to the supply voltage.
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9
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock
The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible input impedance match, such as a typical PC board trace antenna. A nominal value for this inductor with a 50 input impedance is 15nH, but is affected by PC board trace. The LC tank filter connected to LNAOUT comprises L3 and C2 (see the Typical Application Circuit). Select L3 and C2 to resonate at the desired RF input frequency. The resonant frequency is given by: fRF = where: LTOTAL = L3 + LPARASITICS. CTOTAL = C2 + CPARASITICS. LPARASITICS and CPARASITICS include inductance and capacitance of the PC board traces, package pins, mixer input impedance, LNA output impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation should be done to optimize the center frequency of the tank. 1 2 L TOTAL x CTOTAL reduction resistor. The resistor reduces the LNA gain by 35dB, thereby reducing the RSSI output by about 500mV. The LNA resumes high-gain mode when the RSSI level drops back below 1.39V (approximately -70dBm at RF input) for 1ms. The AGC has a hysteresis of 8dB. With the AGC function, the MAX7033 can reliably produce an ASK output for RF input levels up to 0dBm with modulation depth of 18dB. When the AC pin is high and SHDN goes high, the AGC circuit is disabled and the LNA is always in highgain mode. The AGC function can be resumed by bringing the AC pin low when SHDN is high. The MAX7033 features an AGC lock function that is asserted when the level at the AC pin transitions from low to high while SHDN is high. Locking the AGC locks the LNA in the current gain state. As shown in Figure 1, the AGC lock function can be enabled or disabled as long as the SHDN pin is high. Changing the state of AC when SHDN is low has no effect.
MAX7033
Mixer
A unique feature of the MAX7033 is the integrated image rejection of the mixer. This device eliminates the need for a costly front-end SAW filter for most applications. Advantages of not using a SAW filter are increased sensitivity, simplified antenna matching, less board space, and lower cost. The mixer cell is a pair of double balanced mixers that perform an IQ downconversion of the RF input to the 10.7MHz IF from a low-side injected LO (i.e., fLO = fRF fIF). The image-rejection circuit then combines these signals to achieve 44dB of image rejection. Low-side
Automatic Gain Control
When the AC pin is low, the automatic gain-control (AGC) circuit monitors the RSSI output. As the RSSI output reaches 1.98V, which corresponds to RF input level of -62dBm, the AGC switches on the LNA gain
VIH VIL
SHDN PIN
VIH
AC PIN
VIL
AGC LOCK
AGC UNLOCK
AGC LOCK
AGC UNLOCK
NO EFFECT
NO EFFECT AGC DISABLED AGC ENABLED
NO EFFECT AGC DISABLED
AGC ENABLED
Figure 1. AGC Lock Activation Cycles 10 ______________________________________________________________________________________
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033
injection is required due to the on-chip image-rejection architecture. The IF output is driven by a source follower biased to create a driving-point impedance of 330; this provides a good match to the off-chip 330 ceramic IF filter. The IRSEL pin is a logic input that selects one of the three possible image-rejection frequencies. When VIRSEL = 0V, the image rejection is tuned to 315MHz. VIRSEL = VDD5 / 2 tunes the image rejection to 375MHz, and VIRSEL = VDD5 tunes the image rejection to 433MHz. The IRSEL pin is internally set to VDD5 / 2 (image rejection at 375MHz) when it is left unconnected, thereby eliminating the need for an external VDD5 / 2 voltage. where: M = 1 (VXTALSEL = VDD5) or 2 (VXTALSEL = 0V) To allow the smallest possible IF bandwidth (for best sensitivity), minimize the tolerance of the reference crystal.
Intermediate Frequency and RSSI
The IF section presents a differential 330 load to provide matching for the off-chip ceramic filter. The six internal AC-coupled limiting amplifiers produce an overall gain of approximately 65dB, with a bandpass-filter-type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz. The RSSI circuit demodulates the IF by producing a DC output proportional to the log of the IF signal level, with a slope of approximately 14.2mV/dB (see the Typical Operating Characteristics).
Phase-Locked Loop
The PLL block contains a phase detector, charge pump, integrated loop filter, VCO, asynchronous 64x clock divider, and crystal oscillator driver. Besides the crystal, this PLL does not require any external components. The VCO generates a low-side LO. The relationship between the RF, IF, and reference frequencies is given by: f -f fREF = RF IF 32 x M
Applications Information
Crystal Oscillator
The crystal oscillator in the MAX7033 is designed to present a capacitance of approximately 3pF between the XTAL1 and XTAL2. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. Crystals
Table 1. Component Values for Typical Application Circuit
COMPONENT L1 L2 L3 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 R1 X1 X2 VALUE FOR fRF = 433MHz 56nH 15nH 15nH 100pF 2pF 100pF 100pF 1500pF 220pF 470pF 0.47F 220pF 0.01F 0.01F 15pF 15pF 5.1k 6.5984MHz 10.7MHz ceramic filter VALUE FOR fRF = 315MHz 120nH 15nH 27nH 100pF 4pF 100pF 100pF 1500pF 220pF 470pF 0.47F 220pF 0.01F 0.01F 15pF 15pF 5.1k 4.7547MHz 10.7MHz ceramic filter DESCRIPTION TOKO LL1608-FH Murata LQP11A Murata LQP11A 5% 0.1pF 5% 5% 10% 5% 5% 20% 10% 20% 20% Depends on XTAL Depends on XTAL 5% -- Murata SFECV10.7 series
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11
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock
designed to operate with higher differential load capacitance always pull the reference frequency higher. For example, a 4.7547MHz crystal designed to operate with a 10pF load capacitance oscillates at 4.7563MHz with the MAX7033, causing the receiver to be tuned to 315.1MHz rather than 315.0MHz, an error of about 100kHz, or 320ppm. In actuality, the oscillator pulls every crystal. The crystal's natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance. Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: C fP = M 2 1 1 x 106 C + CLOAD CCASE + CSPEC CASE
MAX7033
The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of C5 and C6, use the following equations, along with the coefficients in Table 2: C5 = C6 = b a(100k)( )(fC ) a 4(100k)( )(fC )
where fC is the desired 3dB corner frequency. For example, to choose a Butterworth filter response with a corner frequency of 5kHz: C5 = C6 = 1.000 450pF (1.414)(100k)(3.14)(5kHz) 1.414
(4)(100k)(3.14)(5kHz)
225pF
where: fP is the amount the crystal frequency pulled in ppm. CM is the motional capacitance of the crystal. CCASE is the case capacitance. CSPEC is the specified load capacitance. CLOAD is the actual load capacitance. When the crystal is loaded as specified, i.e., CLOAD = CSPEC, the frequency pulling equals zero. It is possible to use an external reference oscillator in place of a crystal to drive the VCO. AC-couple the external oscillator to XTAL2 with a 1000pF capacitor. Drive XTAL2 with a signal level of approximately -10dBm. ACcouple XTAL1 to ground with a 1000pF capacitor.
Choosing standard capacitor values changes C5 to 470pF and C6 to 220pF, as shown in the Typical Application Circuit.
Data Slicer
The data slicer takes the analog output of the data filter and converts it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. One input is supplied by the data
Table 2. Coefficents to Calculate C5 and C6
FILTER TYPE Butterworth (Q = 0.707) Bessel (Q = 0.577) a 1.414 1.3617 b 1.000 0.618
Data Filter
The data filter is implemented as a 2nd-order lowpass Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency should be set to approximately 1.5 times the fastest expected data rate from the transmitter. Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. The configuration shown in Figure 2 can create a Butterworth or Bessel response. The Butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter.
12
MAX7033
RSSI RDF2 100k RDF1 100k
19 DFO C6
21 OPP C5
22 DFFB
Figure 2. Sallen-Key Lowpass Data Filter
______________________________________________________________________________________
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033
filter output. Both comparator inputs are accessible offchip to allow for different methods of generating the slicing threshold, which is applied to the second comparator input. The suggested data slicer configuration uses a resistor (R1) connected between DSN and DSP with a capacitor (C4) from DSN to DGND (Figure 3). This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The values of R1 and C4 affect how fast the threshold tracks to the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower than the lowest expected data rate. Note that a long string of zeros or ones can cause the threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an equal number of zeros and ones, is used. To prevent continuous toggling of DATAOUT in the absence of an RF signal due to noise, add hysteresis to the data slicer as shown in Figure 4.
MAX7033
DATA SLICER
25 DATAOUT
20 DSN R1
23 DSP
19 DFO
C4
Figure 3. Generating Data Slicer Threshold
MAX7033
DATA SLICER
Peak Detector
The peak-detector output (PDOUT), in conjunction with an external RC filter, creates a DC output voltage equal to the peak value of the data signal. The resistor provides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data-filter output voltage. For faster data slicer response, use the circuit shown in Figure 5.
25 DATAOUT R1 R3 23 DSP 20 DSN R4 19 DFO
R2
*OPTIONAL
C4
Layout Considerations
A properly designed PC board is an essential part of any RF/microwave circuit. On high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are on the order of /10 or longer act as antennas. Keeping the traces short also reduces parasitic inductance. Generally, 1in of a PC board trace adds about 20nH of parasitic inductance. The parasitic inductance can have a dramatic effect on the effective inductance of a passive component. For example, a 0.5in trace connecting a 100nH inductor adds an extra 10nH of inductance or 10%. To reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. Also, use low-inductance connections to ground on all GND pins, and place decoupling capacitors close to all VDD connections.
Figure 4. Generating Data Slicer Hysteresis
MAX7033
DATA SLICER
25 DATAOUT
20 DSN
23 DSP 25k
19 DFO
26 PDOUT
47nF
Figure 5. Using PDOUT for Faster Startup ______________________________________________________________________________________ 13
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033
Typical Application Circuit
+3.3V X1 +3.3V
C11 RF INPUT
C13 1 2 XTAL1 AVDD LNAIN LNASRC AGND LNAOUT AVDD MIXIN1 MIXIN2 AGND IRSEL MIXOUT DGND DVDD X2 IF FILTER C10 IN GND OUT XTAL2 SHDN PDOUT 28 27 26 25 24 23 22 21 20 19 18 17 16 15
C12
C1
L1
3 4
TO/FROM P POWER-DOWN DATA OUT
MAX7033
DATAOUT VDD5 DSP DFFB OPP DSN DFO IFIN2 IFIN1 XTALSEL AC
L2
5 6
R2 R3
+3.3V L3 C3 C2 8 9 C4 C9 11 12 13 14 10 7
C7
R1
C5
C6
C8
COMPONENT VALUES IN TABLE 1
Chip Information
TRANSISTOR COUNT: 3208 PROCESS: CMOS
14
______________________________________________________________________________________
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAX7033
______________________________________________________________________________________
15
315MHz/433MHz ASK Superheterodyne Receiver with AGC Lock MAX7033
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
D2
C L
0.15 C A
D D/2
0.15 C B
b D2/2
0.10M C A B
k
MARKING
XXXXX
E/2 E2/2 E (NE-1)Xe
C L
E2
k L
PIN#1 I.D.
DETAILA
e (ND-1)Xe
PIN#1I.D. 0.35x45 DETAILB
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3 PACKAGEOUTLINE, 16,20,28,32LTHINQFN,5x5x0.8mm
-DRAWINGNOTTOSCALE-
21-0140
F
1
2
COMMONDIMENSIONS PKG. 32L5x5 16L5x5 20L5x5 28L5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20REF. 0 0.02 0.05 0.20REF. 0 0.02 0.05 0.20REF. 0 0.02 0.05 0.20REF. PKG. CODES T1655-1 T1655-2 T1655N-1 T2055-2 T2055-3 T2055-4 T2055-5 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T2855-8 T2855N-1 T3255-2 T3255-3 T3255-4 T3255N-1
EXPOSEDPADVARIATIONS
D2
MIN. NOM. MAX. MIN.
E2
NOM. MAX.
L
0.15
DOWN BONDS ALLOWED
3.00 3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.15 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3.00 3.00 3.00 3.00
3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.10 3.10 3.25 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.20 3.20 3.20 3.35 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80BSC. 0.65BSC. 0.50BSC. 0.50BSC. 0.25 - 0.25 - 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 -
** ** ** ** ** ** 0.40 ** ** ** ** ** ** ** 0.40 ** ** ** ** **
NO YES NO NO YES NO Y NO NO YES YES NO NO YES Y N NO YES NO NO
NOTES: 1.DIMENSIONING&TOLERANCINGCONFORMTOASMEY14.5M-1994. 2.ALLDIMENSIONSAREINMILLIMETERS.ANGLESAREINDEGREES. 3.NISTHETOTALNUMBEROFTERMINALS. 4.THETERMINAL#1IDENTIFIERANDTERMINALNUMBERINGCONVENTIONSHALL CONFORMTOJESD95-1SPP-012.DETAILSOFTERMINAL#1IDENTIFIERARE OPTIONAL,BUTMUSTBELOCATEDWITHINTHEZONEINDICATED.THETERMINAL#1 IDENTIFIERMAYBEEITHERAMOLDORMARKEDFEATURE.
S ** EECOMMONDIMENSIONSTABLE
5.DIMENSIONbAPPLIESTOMETALLIZEDTERMINALANDISMEASUREDBETWEEN0.25mmAND0.30mm FROMTERMINALTIP. 6.NDANDNEREFERTOTHENUMBEROFTERMINALSONEACHDANDESIDERESPECTIVELY. 7.DEPOPULATIONISPOSSIBLEINASYMMETRICALFASHION. 8.COPLANARITYAPPLIESTOTHEEXPOSEDHEATSINKSLUGASWELLASTHETERMINALS. 9.DRAWINGCONFORMSTOJEDECMO220,EXCEPTEXPOSEDPADDIMENSIONFORT2855-1, T2855-3ANDT2855-6. 10.WARPAGESHALLNOTEXCEED0.10mm. 11.MARKINGISFORPACKAGEORIENTATIONREFERENCEONLY. 12.NUMBEROFLEADSSHOWNAREFORREFERENCEONLY. PACKAGEOUTLINE, 16,20,28,32LTHINQFN,5x5x0.8mm
-DRAWINGNOTTOSCALE-
21-0140
F
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
QFN THIN.EPS

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